1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a vertical device and method for conserving layout area on semiconductor chips.
2. Description of the Related Art
In the semiconductor industry, it is advantageous to reduce the size and increase component density on chips. Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device. With device sizes approaching less than 0.2 microns, the decrease in the horizontal dimensions of semiconductor devices has created problems in the operational characteristics of the devices.
To accommodate the conflicting trends of reduced size and increased component density, a need exists for a vertical device which reduces the amount of area occupied of the horizontal plane of the semiconductor device. Such a device would alleviate the conflicting trends. A further need exists for an arrangement of cells in a semiconductor device layout such that an increased density of cells is provided.